Highly Compact Automated Implementation of Linear CA on FPGAs

The current literature on cellular automata (CA) mostly overlooks the fact that the perceived regularity and locality of interconnects in a CA are often logical rather than physical, and difficult to achieve in practical implementations. Optimized mapping, placement and routing of circuits are especially challenging for Field Programmable Gate Array (FPGA) platforms, which often result in low-performance implementations. We develop a design methodology for the automated implementation of low-resource, high-performance CA circuits, by optimal usage of the underlying FPGA architecture, direct primitive instantiation, and constrained placement. Case study for an 1-D CA circuit reveal higher performance, lower hardware resource requirement (by a factor of 0.5 X), acceptable power-delay product (PDP), and superior design scalability, in comparison to implementations derived by standard FPGA CAD tool design flow.

[1]  Palash Sarkar,et al.  A brief history of cellular automata , 2000, CSUR.

[2]  P. Pal Chaudhuri,et al.  Efficient characterisation of cellular automata , 1990 .

[3]  César Torres-Huitzil,et al.  Comparison between 2D cellular automata based pseudorandom number generators , 2012, IEICE Electron. Express.

[4]  Debdeep Mukhopadhyay.  Group Properties of Non-linear Cellular Automata , 2010, J. Cell. Autom..

[5]  Santanu Chattopadhyay,et al.  Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture , 1995, Proceedings of the 8th International Conference on VLSI Design.

[6]  Parimal Pal Chaudhuri,et al.  Architecture for VLSI design of CA based byte error correcting code decoders , 1994, Proceedings of 7th International Conference on VLSI Design.

[7]  Patrick Röder,et al.  FPGA Implementation of Cellular Automata Compared to Software Implementation , 2004, ARCS Workshops.

[8]  Jason Helge Anderson,et al.  Packing Techniques for Virtex-5 FPGAs , 2009, TRETS.

[9]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[10]  Ioannis G. Karafyllidis,et al.  A methodology for VLSI implementation of Cellular Automata algorithms using VHDL , 2001 .

[11]  G. Grewal,et al.  Hierarchical FPGA placement , 2007, Canadian Journal of Electrical and Computer Engineering.

[12]  Andreas Ehliar.  Optimizing Xilinx designs through primitive instantiation , 2010 .

[13]  Jon C. Muzio,et al.  Synthesis of one-dimensional linear hybrid cellular automata , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..