A Jitter Insertion and Accumulation Model for Clock Repeaters

[1]  Paul S. Zuchowski,et al.  Process and environmental variation impacts on ASIC timing , 2004, ICCAD 2004.

[2]  Rajendran Panda,et al.  Vectorless Analysis of Supply Noise Induced Delay Variation , 2003, ICCAD 2003.

[3]  Lawrence T. Pileggi,et al.  Calculating worst-case gate delays due to dominant capacitance coupling , 1997, DAC.

[4]  Anurag Mittal,et al.  Nano-CMOS Circuit and Physical Design , 2004 .

[5]  Lawrence T. Pileggi,et al.  Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Rui L. Aguiar,et al.  A dynamic jitter model to evaluate uncertainty trends with technology scaling , 2012, Integr..

[7]  Wolfgang Maichen Digital Timing Measurements: From Scopes and Probes to Timing and Jitter , 2006 .

[8]  Masanori Hashimoto,et al.  Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise , 2009, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Lawrence T. Pileggi,et al.  A Gate-Delay Model for High-Speed CMOS Circuits , 1994, 31st Design Automation Conference.

[10]  Rui L. Aguiar,et al.  Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis , 2009, PATMOS.

[11]  M. Swaminathan,et al.  Impact of power-supply noise on timing in high-frequency microprocessors , 2002, Electrical Performance of Electronic Packaging,.

[12]  M. Nagata,et al.  Measurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise , 2005, 2005 IEEE Asian Solid-State Circuits Conference.

[13]  Doris Schmitt-Landsiedel,et al.  The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits , 1996, ISLPED '96.

[14]  Lawrence T. Pileggi,et al.  Evaluating RC-interconnect using moment-matching approximations , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[15]  Rui L. Aguiar,et al.  Dynamic jitter accumulation in clock repeaters considering power and ground noise correlations , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[16]  I. Kantorovich,et al.  Maximum Tolerable Power Supply Noise for Data-Clock Synchronization , 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

[17]  C. L. Ratzlaff,et al.  Modeling The RC-interconnect Effects In A Hierarchical Timing Analyzer , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[18]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[19]  Malgorzata Marek-Sadowska,et al.  Buffer delay change in the presence of power and ground noise , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Rajeev Murgai,et al.  An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[21]  W. Burleson,et al.  Period Jitter Estimation in Global Clock Trees , 2008, 2008 12th IEEE Workshop on Signal Propagation on Interconnects.

[22]  P. R. O'Brien,et al.  Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation , 1989, ICCAD 1989.

[23]  Lawrence T. Pileggi,et al.  CMOS gate delay models for general RLC loading , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[24]  Beomsup Kim,et al.  Analysis of timing jitter in CMOS ring oscillators , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.