Conditional speculation and its effects on performance and area for high-level synthesis
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Nikil D. Dutt | Rajesh K. Gupta | Alexandru Nicolau | Sumit Gupta | Nicolae Savoiu | A. Nicolau | Rajesh K. Gupta | N. Dutt | S. Gupta | N. Savoiu
[1] Joseph A. Fisher,et al. Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.
[2] Reinaldo A. Bergamaschi,et al. Behavioral network graph: unifying the domains of high-level and logic synthesis , 1999, DAC '99.
[3] Kemal Ebcioglu,et al. A global resource-constrained parallelization technique , 1989 .
[4] Massoud Pedram,et al. Register Allocation and Binding for Low Power , 1995, 32nd Design Automation Conference.
[5] Wayne Wolf,et al. High-Level VLSI Synthesis , 1991 .
[6] Kazutoshi Wakabayashi,et al. Global scheduling independent of control dependencies based on condition vectors , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[7] Kemal Ebcioglu,et al. An efficient resource-constrained global scheduling technique for superscalar and VLIW processors , 1992, MICRO 1992.
[8] Leon Stok,et al. Module allocation and comparability graphs , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.
[9] Forrest Brewer,et al. A new symbolic technique for control-dependent scheduling , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[10] Minjoong Rim,et al. Global scheduling with code-motions for high-level synthesis applications , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[11] Nikil D. Dutt,et al. Speculation techniques for high level synthesis of control intensive designs , 2001, DAC '01.
[12] Daniel D. Gajski,et al. High ― Level Synthesis: Introduction to Chip and System Design , 1992 .
[13] L. Stok. Transfer free register allocation in cyclic data flow graphs , 1992, [1992] Proceedings The European Conference on Design Automation.
[14] Pierre G. Paulin,et al. Scheduling and Binding Algorithms for High-Level Synthesis , 1989, 26th ACM/IEEE Design Automation Conference.
[15] Niraj K. Jha,et al. Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[16] Jochen A. G. Jess,et al. A reordering technique for efficient code motion , 1999, DAC '99.
[17] Soo-Mook Moon,et al. An efficient resource-constrained global scheduling technique for superscalar and VLIW processors , 1992, MICRO 25.
[18] Alexandru Nicolau,et al. Uniform Parallelism Exploitation in Ordinary Programs , 1985, ICPP.
[19] Massoud Pedram,et al. Module assignment for low power , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.
[20] Donald E. Thomas,et al. Behavioral transformation for algorithmic level IC design , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[21] Kewal K. Saluja,et al. Incorporating performance and testability constraints during binding in high-level synthesis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..