Time-Shared Execution of Realtime Streaming Pipelines by Dynamic Partial Reconfiguration

This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple streaming vision pipelines. The presented time-sharing runtime framework manages an FPGA fabric that can be round-robin time-shared by different pipelines at the time scale of individual frames. In this new use-case, the challenge is to achieve useful performance despite high reconfiguration time. The paper describes the basic runtime support as well as four optimizations necessary to achieve realtime performance giving the constraints of today's FPGAs. The paper provides a characterization of a working runtime framework prototype on a Xilinx ZC706 development board. The paper also reports the performance of a case study where streaming vision pipelines are executed by time-sharing.

[1]  Akash Kumar,et al.  An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[2]  Kizheppatt Vipin,et al.  ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq , 2014, IEEE Embedded Systems Letters.

[3]  Wayne Luk,et al.  Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment , 2015, FPGA.

[4]  Jürgen Becker,et al.  Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration , 2012, Int. J. Reconfigurable Comput..

[5]  Jürgen Teich,et al.  A comparison of embedded reconfigurable video-processing architectures , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[6]  Yu Wang,et al.  EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access , 2015, FPGA.

[7]  Jürgen Becker,et al.  An FPGA run-time system for dynamical on-demand reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[8]  Paul Chow,et al.  FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack , 2014, FCCM 2014.

[9]  Jürgen Teich,et al.  The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer , 2007, J. VLSI Signal Process..

[10]  Walter Stechele,et al.  Autovision – A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision – Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme) , 2007, it Inf. Technol..

[11]  Jim Tørresen,et al.  FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting , 2011, FPGA '11.