2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and 128-row refresh to tolerate short refresh time. Cell is 2X denser than SRAM and is voltage compatible with logic.

[1]  Richard E. Matick,et al.  A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier , 2008, IEEE Journal of Solid-State Circuits.

[2]  P. Bai,et al.  A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[3]  V. De,et al.  A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[4]  Kiyoo Itoh.  Trends in low-voltage embedded-RAM technology , 2002 .

[5]  V. De,et al.  Planar 1T-cell DRAM with MOS storage capacitors in a 130nm logic technology for high density microprocessors caches , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[6]  N. Ikeda,et al.  A novel logic compatible gain cell with two transistors and one capacitor , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[7]  W. M. Regitz,et al.  A three transistor-cell, 1024-bit, 500 NS MOS RAM , 1970 .

[8]  T.N. Blalock,et al.  An experimental 2T cell RAM with 7 ns access time at low temperature , 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.

[9]  N. Vallepalli,et al.  SRAM design on 65nm CMOS technology with integrated leakage reduction scheme , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[10]  Kevin Zhang,et al.  A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.