Program circuit for a phase change memory array with 2 MB/s write throughput for embedded applications

A flexible program circuit for chalcogenide non-volatile memories was developed within a 4Mb ePCM (embedded phase change memory) implemented in 90 nm CMOS technology. The proposed architecture ensures adaptability with respect to process variations and is fully compatible with a single pulse approach or a multiple pulse algorithm for multi-level operation. In the former a write throughput of 2 MB/s is achieved.

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