5-Gb/s linear re-driver in 180 nm CMOS technology

Abstract A single lane, dual channel, 5-Gb/s linear re-driver has been developed and fabricated in low cost 0.18-μm CMOS technology. Some techniques have been applied to attain a very power efficient, low complexity re-driver: transistor optimization, forward scaling design, negative Miller capacitance, and inductive peaking. In addition, the re-driver achieves very good linearity thanks to careful ordering of design blocks. To combat with temperature effect and process variation, some techniques such as ratio-based design and the use of proportional to absolute temperature (PTAT) reference current have also been used. The chip only consumes approximately 90 mA in 5-Gb/s bidirectional operation from a single 1.8 V power supply.