Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous
暂无分享,去创建一个
[1] Ding-Ming Kwai,et al. Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs , 2014, 2014 IEEE 23rd Asian Test Symposium.
[2] W. Gul,et al. Yield aware inter-logic-layer communication in 3-D ICs: Early design stage recommendations , 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).
[3] Sung Kyu Lim,et al. TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Syed Rafay Hasan,et al. Introducing redundant TSV with low inductance for 3-D IC , 2014, 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS).
[5] P. Bar,et al. Use of optical metrology techniques for uniformity Control of 3D stacked IC's , 2014, 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
[6] Tengfei Jiang,et al. Material characterization and failure analysis of through-silicon vias , 2014, Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
[7] Kwang-Seong Choi,et al. Fault isolation of short defect in through silicon via (TSV) based 3D-IC , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).
[8] Sung Kyu Lim,et al. Test-TSV estimation during 3D-IC partitioning , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).
[9] Yanhong Tian,et al. Shearing properties of low temperature Cu-In Solid-Liquid Interdiffusion in 3D package , 2013, 2013 14th International Conference on Electronic Packaging Technology.
[10] Chang Yong Kang,et al. Comprehensive study for RF interference limited 3D TSV optimization , 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
[11] Alexandre Yakovlev,et al. Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[12] Arnaud Virazel,et al. A Study of Tapered 3-D TSVs for Power and Thermal Integrity , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[13] A. S. Oates,et al. An Electromigration Failure Distribution Model for Short-Length Conductors Incorporating Passive Sinks/Reservoirs , 2013, IEEE Transactions on Device and Materials Reliability.
[14] Mallikarjun,et al. Analyzing 3D IC PDNs Using Multiple Clock Domains to Obtain Worst-Case Power Supply Noise and Temperature Variations , 2013 .
[15] Sandeep Kumar Goel. Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[16] Joungho Kim,et al. Disconnection failure model and analysis of TSV-based 3D ICs , 2012, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).
[17] Teng Wang,et al. GALS architecture of H.264 video encoding system on DN-DualV6-PCIe-4 FPGA platform , 2012, 2012 IEEE 11th International Conference on Signal Processing.
[18] Fangming Ye,et al. TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation , 2012, DAC Design Automation Conference 2012.
[19] Qiang Xu,et al. On effective TSV repair for 3D-stacked ICs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[20] Qiang Xu,et al. Yield enhancement for 3D-stacked ICs: Recent advances and challenges , 2012, 17th Asia and South Pacific Design Automation Conference.
[21] Eby G. Friedman,et al. Clock Distribution Networks in 3-D Integrated Systems , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[22] Bashir M. Al-Hashimi,et al. Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs , 2011, 2011 Asian Test Symposium.
[23] Zheng Xu,et al. Parasitics extraction, wideband modeling and sensitivity analysis of through-strata-via (TSV) in 3D integration/packaging , 2011, 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
[24] Zhiyi Yu,et al. Fault tolerant computing for stream DSP applications using GALS multi-core processors , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).
[25] Hsien-Hsin S. Lee,et al. Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[26] Junho Lee,et al. High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV) , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[27] Luca Benini,et al. Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[28] Lorena Anghel,et al. Reliability approach of high density Through Silicon Via (TSV) , 2010, 2010 12th Electronics Packaging Technology Conference.
[29] Sung Kyu Lim,et al. Through-silicon-via management during 3D physical design: When to add and how many? , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[30] Sung Kyu Lim,et al. Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[31] Krishna C. Saraswat,et al. 3-D ICs: Motivation, performance analysis, technology and applications , 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.
[32] Taewhan Kim,et al. Clock tree synthesis with pre-bond testability for 3D stacked IC Designs , 2010, Design Automation Conference.
[33] Sung Kyu Lim,et al. Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs , 2010, SLIP '10.
[34] Ding-Ming Kwai,et al. On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding , 2010, 2010 28th VLSI Test Symposium (VTS).
[35] TingTing Hwang,et al. TSV redundancy: Architecture and design issues in 3D IC , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[36] Young-Hyun Jun,et al. 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.
[37] W. Dehaene,et al. Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.
[38] Ding-Ming Kwai,et al. On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification , 2009, 2009 Asian Test Symposium.
[39] Y. Savaria,et al. A configurable platform for MPSoCs based on application specific instruction set processors , 2009, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.
[40] S. Mukhopadhyay,et al. TSV-aware interconnect length and power prediction for 3D stacked ICs , 2009, 2009 IEEE International Interconnect Technology Conference.
[41] Subarna Sinha,et al. The road to 3D EDA tool readiness , 2009, 2009 Asia and South Pacific Design Automation Conference.
[42] So-Ra Kim,et al. 8Gb 3D DDR3 DRAM using through-silicon-via technology , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[43] Zhiyi Yu,et al. High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[44] Ravi Jenkal,et al. Inter-die signaling in three dimensional integrated circuits , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[45] E.G. Friedman,et al. Clock distribution architectures for 3-D SOI integrated circuits , 2008, 2008 IEEE International SOI Conference.
[46] Daniel Arumí,et al. Experimental Characterization of CMOS Interconnect Open Defects , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[47] A. Jourdain,et al. 3D stacked IC demonstration using a through Silicon Via First approach , 2008, 2008 IEEE International Electron Devices Meeting.
[48] Eckhard Grass,et al. Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook , 2007, IEEE Design & Test of Computers.
[49] Sandeep K. Shukla,et al. Guest Editors' Introduction: GALS Design and Validation , 2007, IEEE Design & Test of Computers.
[50] Guy Lemieux,et al. A Survey and Taxonomy of GALS Design Styles , 2007, IEEE Design & Test of Computers.
[51] Luca Benini,et al. Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[52] Xin Wang,et al. A RTL Asynchronous FIFO Design Using Modified Micropipeline , 2006, 2006 International Biennial Baltic Electronics Conference.
[53] Zhiyi Yu,et al. Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles , 2006, 2006 International Conference on Computer Design.
[54] Alain J. Martin,et al. Asynchronous Techniques for System-on-Chip Design , 2006, Proceedings of the IEEE.
[55] Xiaohua Kong,et al. High-speed reduced stack dual lock circuits , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..
[56] Marcos Ferretti,et al. SINGLE-TRACK ASYNCHRONOUS PIPELINE TEMPLATE , 2004 .
[57] Michael L. Scott,et al. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.
[58] Eby G. Friedman,et al. Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.
[59] Kaustav Banerjee,et al. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.
[60] Ivan E. Sutherland,et al. GasP: a minimal FIFO control , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.
[61] Christer Svensson,et al. Self-tested self-synchronization circuit for mesochronous clocking , 2001 .
[62] A. S. Oates,et al. Monte-Carlo simulation of electromigration failure distributions of submicron contacts and vias: a new extrapolation methodology for reliability estimate , 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).
[63] Hannu Tenhunen,et al. Globally asynchronous locally synchronous architecture for large high-performance ASICs , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[64] Christer Svensson,et al. Self-tested self-synchronization by a two-phase input port , 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).
[65] David Jones. High performance , 1989, Nature.