A low-latency software-based route lookup implementation for network processors

Edge and access routers require fast and flexible route table lookup for incoming IP packets at relatively low cost. However, today's most NPs are not optimized for basic route lookup operations and tend to offload them to expensive TCAM or dedicated search engine. This paper describes a software-based route cache utilizing on-chip SRAM of NP. Accessing high-speed on-chip SRAM instead of long-latency off-chip DRAM can effectively reduce the average search time, eliminating the demand of TCAM and making more headroom for other applications. One of the major design issues is selecting a suitable hash function to make a balance between conflict miss rate and update complexity. The detailed implementation of the program can take advantage of optimized instruction set of NP. Experiments with real-life packet traces show that a high bit rate can be easily achieved with a small SRAM.

[1]  Hao Che,et al.  A flow caching mechanism for fast packet forwarding , 2002, Comput. Commun..

[2]  Bill Lin,et al.  IP caching for terabit speed routers , 1999, Seamless Interconnection for Universal Services. Global Telecommunications Conference. GLOBECOM'99. (Cat. No.99CH37042).

[3]  Tzi-cker Chiueh,et al.  Cache Memory Design for Internet Processors , 2000, IEEE Micro.

[4]  Cheng-Shong Wu,et al.  Multilevel aligned IP prefix caching based on singleton information , 2002, Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.

[5]  Patrick Crowley,et al.  Network Processor Design: Issues and Practices , 2002 .

[6]  Mukesh Singhal,et al.  A novel cache architecture to support layer-four packet classification at memory access speeds , 2000, Proceedings IEEE INFOCOM 2000. Conference on Computer Communications. Nineteenth Annual Joint Conference of the IEEE Computer and Communications Societies (Cat. No.00CH37064).

[7]  Tzi-cker Chiueh,et al.  Improving Route Lookup Performance Using Network Processor Cache , 2002, ACM/IEEE SC 2002 Conference (SC'02).

[8]  John William Marshall.  Chapter 11 – Cisco Systems–Toaster2 , 2003 .

[9]  Huan Liu,et al.  Routing prefix caching in network processor design , 2001, Proceedings Tenth International Conference on Computer Communications and Networks (Cat. No.01EX495).

[10]  Tzi-cker Chiueh,et al.  High-performance IP routing table lookup using CPU caching , 1999, IEEE INFOCOM '99. Conference on Computer Communications. Proceedings. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. The Future is Now (Cat. No.99CH36320).

[11]  Kang Li,et al.  Architectures for packet classification caching , 2003, The 11th IEEE International Conference on Networks, 2003. ICON2003..

[12]  Nick McKeown,et al.  Routing lookups in hardware at memory access speeds , 1998, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.