Statistical rare event analysis using smart sampling and parameter guidance

In this paper, we propose a new efficient statistical method for failure probability estimation of analog circuits with rate failure events, which is a time-consuming process using the existing Monte Carlo method. On top of this, the new method can also provide the estimation of parameter regions to achieve targeted performance to facilitate the design process, which is missing in the traditional fast statistical methods such as the statistical blockage based method. The new method employs two new techniques to speed up the analysis. First, to reduce the large number of samples for rare event analysis, the new approach employs a smart sample selection scheme, which can consider the effectiveness of samples and well-coverage for the parameter space. As a result, it can reduce an additional simulation costs by pruning less effective samples while keeping the accuracy of failure estimation. Second, the new approach identifies the failure regions in terms of parameters to provide a good design guideline for designers and optimization tools. This is enabled by applying the variance based feature selection to find the dominant parameters. A quasi-random sampling with dominant parameters is then applied to determine in-spec boundaries of those parameters. In addition, we also provide the complete formula for the probability determinations of failure regions in the iterative failure region searching framework. We demonstrate the advantage of our proposed method using two test benches: 6T-SRAM reading failure diagnosis with 27 process parameters, charge pump operation failure diagnosis in a PLL circuit with 81 process parameters. Experimental results show that the new method can be 4X more accurate than the recently proposed REscope method. Furthermore, the new method reduces the simulation cost by 2X than the recursive statistical blockage (RSB) method with same accuracy level. Our approach also provides the precise guidance of diverse parameters with 1.21% estimation error.

[1]  Rajiv V. Joshi,et al.  Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[2]  Robert Tibshirani,et al.  The Elements of Statistical Learning: Data Mining, Inference, and Prediction, 2nd Edition , 2001, Springer Series in Statistics.

[3]  Lara Dolecek,et al.  Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[4]  J. Hosking,et al.  Parameter and quantile estimation for the generalized pareto distribution , 1987 .

[5]  Rob A. Rutenbar,et al.  Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Kaushik Roy,et al.  Statistical design and optimization of SRAM cell for yield enhancement , 2004, ICCAD 2004.

[7]  Rob A. Rutenbar,et al.  Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design , 2008, 21st International Conference on VLSI Design (VLSID 2008).

[8]  Frances Y. Kuo,et al.  Remark on algorithm 659: Implementing Sobol's quasirandom sequence generator , 2003, TOMS.

[9]  Sani R. Nassif,et al.  Statistical analysis of SRAM cell stability , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  J. Hosking Maximum‐Likelihood Estimation of the Parameters of the Generalized Extreme‐Value Distribution , 1985 .

[11]  Timothy N. Trick,et al.  A Study of Variance Reduction Techniques for Estimating Circuit Yields , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Atsushi Kurokawa,et al.  Challenge: variability characterization and modeling for 65- to 90-nm processes , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[13]  Rob A. Rutenbar,et al.  Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS , 2008, Proceedings of the IEEE.

[14]  Wei Wu,et al.  REscope: High-dimensional statistical circuit simulation towards full failure region coverage , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[15]  Wei Wu,et al.  A fast and provably bounded failure analysis of memory circuits in high dimensions , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).