Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
暂无分享,去创建一个
[1] Kiyoung Choi,et al. Narrow bus encoding for low power systems , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).
[2] Mircea R. Stan,et al. Low-power encodings for global communication in CMOS VLSI , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[3] Peter P. Pham,et al. A low power differential bus utilizing novel split level bus technique , 1990, Proceedings on Bipolar Circuits and Technology Meeting.
[4] Wei-Chung Cheng,et al. Power-optimal encoding for a DRAM address bus , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[5] Dake Liu,et al. Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.
[6] Jan M. Rabaey,et al. A partitioning scheme for optimizing interconnect power , 1997, IEEE J. Solid State Circuits.
[7] K. Asada,et al. Bus data encoding with coupling-driven adaptive code-book method for low power data transmission , 2001, Proceedings of the 27th European Solid-State Circuits Conference.
[8] Anantha P. Chandrakasan,et al. Low power bus coding techniques considering inter-wire capacitances , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
[9] Wei-Chung Cheng,et al. Power-optimal encoding for DRAM address bus (poster session) , 2000, ISLPED '00.
[10] Mircea R. Stan,et al. Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[11] Hiroto Yasuura,et al. A bus delay reduction technique considering crosstalk , 2000, DATE '00.
[12] Luca Benini,et al. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems , 1997, Proceedings Great Lakes Symposium on VLSI.
[13] Anantha Chandrakasan,et al. Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[14] Chi-Ying Tsui,et al. Saving power in the control path of embedded processors , 1994, IEEE Design & Test of Computers.
[15] Tomás Lang,et al. Exploiting the locality of memory references to reduce the address bus energy , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.
[16] Naresh R. Shanbhag,et al. A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[17] Kevin Skadron,et al. Odd/even bus invert with two-phase transfer for buses with coupling , 2002, ISLPED '02.
[18] A. Matsuzawa,et al. A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme , 1996 .
[19] T. Sakurai,et al. Two schemes to reduce interconnect delay in bi-directional and uni-directional buses , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
[20] Takayasu Sakurai,et al. Coupling-driven bus design for low-power application-specific systems , 2001, DAC '01.
[21] Rajesh Kumar,et al. Interconnect and noise immunity design for the Pentium 4 processor , 2003, DAC.
[22] Kiyoung Choi,et al. Partial bus-invert coding for power optimization of system level bus , 1998, ISLPED '98.
[23] Sung-Mo Kang,et al. Coupling-driven signal encoding scheme for low-power interface design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[24] Jamil Kawa,et al. Modeling and analysis of differential signaling for minimizing inductive cross-talk , 2001, DAC '01.