Metal gate VT modulation using PLAD N2 implants for Ge p-FinFET applications

This work reports multi-VT Ge gate stacks using low energy plasma-assisted doping (PLAD) with N2 for Ge p-FinFET applications. Varying implant dose and energy is used to demonstrate effective TiN work-function tuning over a range of 170 mV from near-midgap to near-valence band edge of Ge without significant impact on gate capacitance (effective oxide thickness (EOT)), interface quality and TiN resistance. However, unlike Si gate stacks, increased gate leakage in implanted samples is likely due to traps created in the HfO2 Hi-k layer and exposed to channel carriers due to a low band offset GeO2 interfacial layer.

[1]  A. Nainani,et al.  Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation , 2013 .

[2]  J. L. Hartke.  The Three‐Dimensional Poole‐Frenkel Effect , 1968 .

[3]  M Takenaka,et al.  High-Performance $\hbox{GeO}_{2}/\hbox{Ge}$ nMOSFETs With Source/Drain Junctions Formed by Gas-Phase Doping , 2010, IEEE Electron Device Letters.

[4]  Hsing-Huang Tseng,et al.  Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High-$k$/Metal Gates CMOS FinFETs for Multi- $V_{\rm Th}$ Engineering , 2010, IEEE Transactions on Electron Devices.

[5]  G. Dewey,et al.  High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture , 2010, 2010 International Electron Devices Meeting.

[6]  Shimeng Yu,et al.  Conduction mechanism of TiN/HfOx/Pt resistive switching memory: A trap-assisted-tunneling model , 2011 .

[7]  E. Simoen,et al.  Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes , 2013, 2013 Symposium on VLSI Technology.

[8]  Peter Kulchyski.  and , 2015 .

[9]  N. Collaert,et al.  Treshold voltage modulation in FinFET devices through Arsenic Ion Implantation into TiN/HfSiON gate stack , 2007, 2007 IEEE International SOI Conference.

[10]  Che-Wei Chang,et al.  Electron conduction mechanism and band diagram of sputter-deposited Al∕ZrO2∕Si structure , 2005 .

[11]  Enhanced Ge n+/p Junction Performance Using Cryogenic Phosphorus Implantation , 2015, IEEE Transactions on Electron Devices.

[12]  B. Parvais,et al.  Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[13]  A. Stesmans,et al.  Trap-assisted tunneling in high permittivity gate dielectric stacks , 2000 .