Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts

A new kind of a decision diagrams are presented: its nodes correspond to all types of nonsingular expansions for groups of input variables, in particular pairs. The diagrams are called the Linearly Independent (LI) Decision Diagrams (LI DDs). There are 840 nonsigular expansions for a pair of variables, thus 840 different types of nodes in the tree. Therefore, the number of nodes in such (exact) diagrams is usually much smaller than the number of nodes in the well-known Kronecker diagrams (which have only single-variable Shannon, Positive Davio, and Negative Davio expansions in nodes). It is usually much smaller than 1/3 of the number of nodes in Kronecker diagrams. Similarly to Kronecker diagrams, the LI Diagrams are a starting point to a synthesis of multilevel AND/OR/EXOR circuits with regular structures. Other advantages of LI diagrams include: they generalize the well-known Pseudo-Kronecker Functional Decision Diagrams, and can be used to optimize the new type of PLAs called LI PLAs. Importantly, while the known decision diagrams used AND/EXOR or AND/OR bases, the new diagrams are AND/OR/EXOR-based. Thus, because of a larger design space, multi-level structures of higher regularity can be created with them. This paper presents both new concepts and new efficient synthesis algorithms.

[1]  Marek A. Perkowski,et al.  Fast minimization of mixed-polarity AND/XOR canonical networks , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[2]  M. Perkowski,et al.  Multiple valued input generalised Reed-Muller forms , 1992 .

[3]  Marek A. Perkowski.  The generalized orthonormal expansion of functions with multiple-valued inputs and some of its applications , 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.

[4]  Liam P. Maguire,et al.  State assignment techniques in multiple-valued logic , 1999, Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329).

[5]  Marek A. Perkowski,et al.  A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms , 1988, DAC '88.

[6]  D. Green.  Families of Reed-Muller canonical forms , 1991 .

[7]  Marek A. Perkowski,et al.  Free Kronecker Decision Diagrams and their Application to Atmel 6000 FPGA Mapping , 1995 .

[8]  Rolf Drechsler,et al.  Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.

[9]  Tsutomu Sasao,et al.  GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions , 1995, ASP-DAC '95.

[10]  Susanto Rahardja,et al.  Classification and properties of fast linearly independent logic transformations , 1997 .

[11]  M. A. Perkowski,et al.  Canonical multi-valued input Reed-Muller trees and forms , 1991 .

[12]  Rolf Drechsler,et al.  New hierarchies of AND/EXOR trees, decision diagrams, lattice diagrams, canonical forms and regular layouts , 1997 .

[13]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[14]  Rolf Drechsler,et al.  Pseudo Kronecker expressions for symmetric functions , 1997, Proceedings Tenth International Conference on VLSI Design.

[15]  Rolf Drechsler,et al.  A canonical AND/EXOR form that includes both the generalized Reed-Muller forms and Kronecker forms , 1997 .

[16]  Rolf Drechsler,et al.  Ternary and quaternary lattice diagrams for linearly-independent logic, multiple-valued logic, and analog synthesis , 1997, Proceedings of ICICS, 1997 International Conference on Information, Communications and Signal Processing. Theme: Trends in Information Systems Engineering and Wireless Multimedia Communications (Cat..

[17]  Malgorzata Marek-Sadowska,et al.  Wave steering in YADDs: a novel non-iterative synthesis and layout technique , 1999, DAC '99.

[18]  Tsutomu Sasao,et al.  Representations of Logic Functions Using EXOR Operators , 1996 .

[19]  Malgorzata Marek-Sadowska,et al.  Logic Synthesis for Testability , 1996, Great Lakes Symposium on VLSI.

[20]  Tsutomu Sasao,et al.  Optimization of multiple-valued AND-EXOR expressions using multiple-place decision diagrams , 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.

[21]  Munehiro Matsuura,et al.  Multi-level Logic Synthesis Based on Pseudo-Kronecker Decision Diagrams and Local Transformation , 1995 .

[22]  Malgorzata Chrzanowska-Jeske,et al.  Lattice Diagrams Using Reed-Muller Logic , 1997 .

[23]  T. Sasao,et al.  GRMIN2: A heuristic simplification algorithm for generalised Reed-Muller expressions , 1996 .

[24]  Marek A. Perkowski,et al.  EXORCISM-MV-2: minimization of exclusive sum of products expressions for multiple-valued input incompletely specified functions , 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.

[25]  M. Chrzanowska-Jeske,et al.  A regular representation for mapping to fine-grain, locally-connected FPGAs , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[26]  Rolf Drechsler,et al.  Synthesis of pseudo Kronecker lattice diagrams , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[27]  Marek Perkowski,et al.  Design For Testability Properties of AND/XOR Networks , 1993 .

[28]  Bernhard Eschermann,et al.  Module generation for AND/XOR-fields (XPLAs) , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[29]  Marek Perkowski,et al.  Two learning methods for a tree-search combinatorial optimizer , 1990, Ninth Annual International Phoenix Conference on Computers and Communications. 1990 Conference Proceedings.

[30]  Susanto Rahardja,et al.  Fast transforms for orthogonal logic , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[31]  Malgorzata Chrzanowska-Jeske,et al.  A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays , 1994, 31st Design Automation Conference.

[32]  Jean-Pierre Deschamps,et al.  Discrete and switching functions , 1978 .

[33]  Marek A. Perkowski,et al.  Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[34]  R. Drechsler,et al.  Ordered and shared, linearly-independent, variable-pair decision diagrams , 1997, Proceedings of ICICS, 1997 International Conference on Information, Communications and Signal Processing. Theme: Trends in Information Systems Engineering and Wireless Multimedia Communications (Cat..

[35]  Marek A. Perkowski,et al.  Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..