Routing algorithm for multi-FPGA based systems using multi-point physical tracks

Multi-FPGA boards suffer from large timing delays in inter-FPGA physical tracks compared to intra-FPGA track delays, as well as a limited bandwidth between FPGAs due to the limited number of I/Os per FPGA. In order to tackle this problem, an algorithm which routes multi-terminal nets in multi-point tracks is proposed in this paper to spare FPGA I/Os. Experiments are conducted using Gaisler Research Benchmarks. Firstly, each testbench will be implemented in an off-the-shelf board. The results show that the system frequency can be increased in the off-the-shelf board by the proposed routing algorithm. Secondly, an automatic design flow which generates a custom multi-FPGA board is enhanced by generating multi-point tracks in the board, and each testbench will be implemented with the proposed routing algorithm in custom boards. The results show that the system frequency is improved in the custom board with both 2- and multi-point tracks.

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