A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC

A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption and small die area by sharing an opamp between two successive pipeline stages. Further reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique. The ADC, implemented in a 0.18-mum dual-gate-oxide (DGO) CMOS technology, achieves 72.4-dB signal-to-noise and distortion ratio, 88.5-dB spurious free dynamic range, and 11.7 effective number of bits at full sampling rate with a 46-MHz input while consuming 230-mW from a 3-V supply.

[1]  J. Arias,et al.  Low-power pipeline ADC for wireless LANs , 2004, IEEE Journal of Solid-State Circuits.

[2]  Michiel Steyaert,et al.  Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages , 1994, IEEE J. Solid State Circuits.

[3]  T. L. Sculley,et al.  A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter , 2002 .

[4]  M. Yoshioka,et al.  A 10 b 125 MS/s 40 mW pipelined ADC in 0.18 /spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[5]  I. Mehr,et al.  A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 1999, IEEE Journal of Solid-State Circuits.

[6]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[7]  Andrew Morgan,et al.  A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[8]  Kari Halonen,et al.  1-V 9-bit pipelined switched-opamp ADC , 2001 .

[9]  Seung-Chul Lee,et al.  A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  P.R. Gray,et al.  A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR , 2004, IEEE Journal of Solid-State Circuits.

[11]  Seung-Hoon Lee,et al.  A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors , 2006, IEEE Custom Integrated Circuits Conference 2006.

[12]  T. Kuyel,et al.  A 14 b 40 MSample/s pipelined ADC with DFCA , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[13]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[14]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[15]  Wenhua Yang,et al.  A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input , 2001, IEEE J. Solid State Circuits.

[16]  Zheng Liu,et al.  A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique , 2007, 2007 IEEE Symposium on VLSI Circuits.

[17]  Dong-Young Chang.  Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[18]  Dong-Young Chang,et al.  A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique , 2003 .

[19]  Stephen H. Lewis,et al.  A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers , 1997, IEEE J. Solid State Circuits.

[20]  K. Bacrania,et al.  A 14-b linear capacitor self-trimming pipelined ADC , 2004, IEEE Journal of Solid-State Circuits.

[21]  Hae-Seung Lee,et al.  A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[22]  A.M.A. Ali,et al.  A 100-dB SFDR 80-MSPS 14-Bit 0.35-$ muhbox m$BiCMOS Pipeline ADC , 2006, IEEE Journal of Solid-State Circuits.

[23]  Deog-Kyoon Jeong,et al.  A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Byung-Moo Min,et al.  A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC , 2003, IEEE J. Solid State Circuits.

[25]  C. Schwoerer,et al.  An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[26]  H. Matsui,et al.  A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s , 2006, IEEE Journal of Solid-State Circuits.