A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch

This paper proposes a highly-dense reconfigurable architecture that introduces via-switch device, which is a kind of resistive RAM and is used in crossbar switches. Since via-switch is implemented in BEOL layers only, the FEOL layer under the crossbar can be fully exploited for highly-dense logic blocks. The proposed architecture uses the FEOL layer for fine-grained look-up tables and coarse-grained arithmetic/memory units for better performance and highly wide applications. In a case study of application mapping, the proposed architecture reduces array area by 76% thanks to mixed grained logic structure and overlay bidirectional interconnection. Thanks to 18F2 footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by 26× and the delay and energy in the interconnection are reduced by 90% and 93% at 0.5V operation.

[1]  Vaughn Betz,et al.  The stratixπ routing and logic architecture , 2003, FPGA '03.

[2]  Abbas El Gamal,et al.  Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory , 2012, 2012 IEEE International Solid-State Circuits Conference.

[3]  Toshitsugu Sakamoto,et al.  Improved Off-State Reliability of Nonvolatile Resistive Switch With Low Programming Voltage , 2012, IEEE Transactions on Electron Devices.

[4]  Toshitsugu Sakamoto,et al.  Low-power programmable-logic cell arrays using nonvolatile complementary atom switch , 2014, Fifteenth International Symposium on Quality Electronic Design.

[5]  Toshitsugu Sakamoto,et al.  0.5-V Highly Power-Efficient Programmable Logic using Nonvolatile Configuration Switch in BEOL , 2015, FPGA.

[6]  Wei Wang,et al.  FPGA Based on Integration of CMOS and RRAM , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Jason Cong,et al.  FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Mingjie Lin,et al.  Performance Benefits of Monolithically Stacked 3-D FPGA , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Kazutoshi Wakabayashi,et al.  C-based SoC design flow and EDA tools: an ASIC and system vendorperspective , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Jonathan Rose,et al.  Measuring the Gap Between FPGAs and ASICs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  N. Banno,et al.  A novel two-varistors (a-Si/SiN/a-Si) selected complementary atom switch (2V-1CAS) for nonvolatile crossbar switch with multiple fan-outs , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[12]  Hiroyuki Ochi,et al.  Area-efficient LUT-like programmable logic using atom switch and its mapping algorithm , 2015, 2015 15th International Symposium on Communications and Information Technologies (ISCIT).

[13]  Giovanni De Micheli,et al.  A high-performance low-power near-Vt RRAM-based FPGA , 2014, 2014 International Conference on Field-Programmable Technology (FPT).

[14]  G. De Micheli,et al.  Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs , 2013, IEEE Transactions on Nanotechnology.

[15]  Masato Motomura,et al.  Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[16]  T. Sakamoto,et al.  Polymer Solid-Electrolyte Switch Embedded on CMOS for Nonvolatile Crossbar Switch , 2011, IEEE Transactions on Electron Devices.

[17]  H. Hada,et al.  Nonvolatile Crossbar Switch Using $\hbox{TiO}_{x}/ \hbox{TaSiO}_{y}$ Solid Electrolyte , 2010, IEEE Transactions on Electron Devices.

[18]  Toshitsugu Sakamoto,et al.  Improved ON-State Reliability of Atom Switch Using Alloy Electrodes , 2013, IEEE Transactions on Electron Devices.