Functional-Level Hardware Simulation with Pull-Model Data Flow

NA

[1]  Patt.  Introduction to Computing Systems , 2001 .

[2]  Klaus D. Müller-Glaser,et al.  Advanced optimistic approaches in logic simulation , 1998, Proceedings Design, Automation and Test in Europe.

[3]  Andrew W. Appel.  Simulating digital circuits with one bit per wire , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Daniel Weise,et al.  Automatic generation of compiled simulations through program specialization , 1991, 28th ACM/IEEE Design Automation Conference.

[5]  Jun Wang,et al.  Compiled Code in Distributed Logic Simulation , 2006, Proceedings of the 2006 Winter Simulation Conference.

[6]  Peter M. Maurer.  The Inversion Algorithm for digital simulation , 1994, ICCAD '94.

[7]  Roger D. Chamberlain,et al.  Parallel Logic Simulation of VLSI Systems , 1995, 32nd Design Automation Conference.

[8]  David M. Lewis.  A hierarchical compiled code event-driven logic simulator , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Karem A. Sakallah,et al.  Ravel: assinged-delay compiled-code logic simulation , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.