Hyperactive Faults Dictionary to Increase Diagnosis Throughput

For volume production of VLSI designs in future technologies fast and accurate diagnosis of manufacturing defects on a large number of chips is necessary to ramp up yields. Methods to speed up commonly used effect-cause fault diagnosis procedures have been recently proposed. These include the use of fault response dictionary. However, for very large industrial designs, these methods either need very large dictionaries or they drastically reduce the speedup achievable by using dictionaries. In this work we propose a method to achieve higher speedup with small sized dictionaries. We achieve this by identifying a set of faults called hyperactive faults for which we create a novel dictionary. Experimental results are presented to demonstrate the effectiveness of the proposed method.

[1]  Leendert M. Huisman,et al.  Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[2]  Sudhakar M. Reddy,et al.  Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[3]  S.M. Reddy,et al.  Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead , 2007, 16th Asian Test Symposium (ATS 2007).

[4]  Vamsi Boppana,et al.  Full fault dictionary storage based on labeled tree encoding , 1996, Proceedings of 14th VLSI Test Symposium.

[5]  Janusz Rajski,et al.  Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement , 2007, 12th IEEE European Test Symposium (ETS'07).

[6]  Camelia Hora,et al.  Systematic defects in deep sub-micron technologies , 2004, 2004 International Conferce on Test.

[7]  Janusz Rajski,et al.  A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis , 2006, 2006 IEEE International Test Conference.

[8]  Irith Pomeranz,et al.  On the generation of small dictionaries for fault location , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[9]  Tracy Larrabee,et al.  Creating small fault dictionaries [logic circuit fault diagnosis] , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[11]  Chris Schuermyer,et al.  Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis , 2005, IEEE International Conference on Test, 2005..

[12]  Camelia Hora,et al.  An effective diagnosis method to support yield improvement , 2002, Proceedings. International Test Conference.

[13]  Sungju Park,et al.  Why is less information from logic simulation more useful in fault simulation? , 1990, Proceedings. International Test Conference 1990.

[14]  T. Larrabee Creating Small Fault Dictionaries , 1998 .

[15]  C. Burmer,et al.  Yield enhancement through fast statistical scan test analysis for digital logic , 2005, IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005..