Hardware-Software Co-design for Reconfigurable Field Programmable Gate Arrays Using Mixed-Integer Programming

Hardware-Software Co-design for Reconfigurable Field Programmable Gate Arrays Using Mixed-Integer Programming

[1]  Aravind Dasu,et al.  Reconfigurable media processing , 2002, Parallel Comput..

[2]  J.R. Cavallaro,et al.  A General Hardware/Software Co-design Methodology for Embedded Signal Processing and Multimedia Workloads , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[3]  Florian Dittmann,et al.  Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[4]  J. Teich,et al.  A system-level approach to hardware reconfigurable systems , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[5]  Rajesh Gupta,et al.  Hardware/software co-design , 1996, Proc. IEEE.

[6]  K. Shibata,et al.  Codesign methodology on programmable hardware and software system , 1994, Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems.

[7]  A. Shoba Das,et al.  Hardware-software co-synthesis of hard real-time systems with reconfigurable FPGAs , 2004, Comput. Electr. Eng..

[8]  Armin Bender,et al.  Design of an optimal loosely coupled heterogeneous multiprocessor system , 1996, Proceedings ED&TC European Design and Test Conference.

[9]  Martin D. F. Wong,et al.  Integrated partitioning and scheduling for hardware/software co-design , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[10]  Marshall L. Fisher,et al.  A dual algorithm for the one-machine scheduling problem , 1976, Math. Program..

[11]  Hanif D. Sherali,et al.  Improving Discrete Model Representations via Symmetry Considerations , 2001, Manag. Sci..

[12]  Kiyoung Choi,et al.  Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[13]  P. Arato,et al.  Hardware-software partitioning in embedded system design , 2003, IEEE International Symposium on Intelligent Signal Processing, 2003.

[14]  Moshe Sipper,et al.  Configurable Chips Meld Software and Hardware , 2000, Computer.

[15]  Kiyoung Choi,et al.  Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign , 1997, CODES.

[16]  Michael Pinedo,et al.  Scheduling: Theory, Algorithms, and Systems , 1994 .

[17]  Álvaro Suárez Sarmiento,et al.  Pipelining-based tradeoffs for hardware/software codesign of multimedia systems , 2000, Proceedings 8th Euromicro Workshop on Parallel and Distributed Processing.

[18]  Peter Marwedel,et al.  An Algorithm for Hardware/Software Partitioning Using Mixed Integer Linear Programming , 1997, Des. Autom. Embed. Syst..

[19]  Jonathan Saul.  Hardware/software codesign for FPGA-based systems , 1999, Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences. 1999. HICSS-32. Abstracts and CD-ROM of Full Papers.

[20]  M. D. Edwards,et al.  Hardware/software partitioning for performance enhancement , 1995 .