Two phase simulation-based assessment of quantum error correction codes

This paper proposes a VHDL-based simulation technique for studying the effects of noise on fault tolerant quantum circuits using fault injection. We aimed at an accurate fault modeling using a Hardware Description Language CAD environment that yields relevant results. However, the resources needed for simulated fault injection become prohibitive with the growth of the circuit (i.e. for the worst case simulation resources grow exponentially with the number of qubits). Furthermore, the fault tolerant mechanisms rely on quantum error correction codes and concatenated coding that further increase the complexity of the analyzed circuit. We address these problems, by proposing a multi-phase approach, based on a two-phase simulation for assessing fault tolerance. In the first phase, the basic blocks of the encoded circuit are analyzed with the simulated fault injection methodology, yielding the noise parameters needed during the second phase, when the logical circuit is analyzed. We show that this approach yields a good approximation for noise values lower than 10−2.