Workshop Report: VLSI Development Techniques

"Testability is what you promise the customer that you will build into a system , but it is the first thing to go when the going gets tough." How to deal with this early test maxim was just one of the subjects addressed at the Twelfth Annual Computer Elements Committee Workshop, held in Mesa, Arizona, November 30-December 3. Meeting to discuss emerging device technologies for the 80's, some 82 representatives from 30 companies and universities participated in the workshop, which opened with a keynote session on "The Architectural and Design Considerations for a Satellite System Employing Time Division Multiple-Access Techniques. " Speakers at this session stressed the system , technology, and schedule tradeoffs that have to be considered in designing such a system-one that uses a relatively expensive fixed-bandwidth transmission channel. These tradeoffs can affect such things as voice quality, buffer storage, and frame synchronization design parameters. Performance evaluation of network elements using CMOS shows them to be compatible with high-speed array processors for military applications. As a result, signal processing architectures may take a more distributed form in the future. (Examples of military, imaging, and medical applications were discussed at the conference.) Medical signal-processing needs, which tend to equal or exceed those of present-day military requirements in speed and computational complexity, are likely to parallel those in the military arena. This parallel will most readily be seen in the design of special-purpose, high-speed computers-used in devices such as CAT scanners that are comparable to image processing mainframe elements. This session included discussions of 10-to 14-MIP general-purpose computers and a high-performance military signal processor. The 14-MIP machine achieved 350-ps propagation delays and chip densities of 1300 gates using forced-air cooling across finned heat studs. In the military machine, packaged chip heat stacks are held in copper collets within an air-cooled channel. Both of these cooling approaches achieve thermal impedences of about 6°C per watt (junction to air). Another approach to thermal and in-terconnection packaging uses a unique helium/water-cooled module containing 1 18 chips and dissipating about 100 watts. With this technique, thermal resistances of 8-9°C per watt are possible. Module in-terconnection is achieved with a high-density PCB, but chip interconnection resides in a 33-layer ceramic board.