论文信息 - A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS

A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS

ADPLL frequency synthesizers have recently drawnsignificant research attention as the technology paradigm shifts into the nanometer CMOS arena [1–5]. They circumvent several design issues that conventional charge-pump-based PLLs encounter, including capacitor leakage, current mismatch, and limited dynamic range. Furthermore, they benefit from replacing the bulky passive loop filter by a more cost-effective and flexible digital filter.

Wei-Zen Chen | Song-Yu Yang

[1] P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[2] P. Gregorius,et al. A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS , 2005, IEEE Journal of Solid-State Circuits.

[3] Matthew Z. Straayer,et al. A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4] Matthew Z. Straayer,et al. A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, IEEE Journal of Solid-State Circuits.

[5] Ping-Ying Wang,et al. A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6] J.A. Tierno,et al. A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI , 2008, IEEE Journal of Solid-State Circuits.

[7] K. Muhammad,et al. All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.