System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic
暂无分享,去创建一个
[1] Federico Angiolini,et al. /spl times/pipes Lite: a synthesis oriented design library for networks on chips , 2005, Design, Automation and Test in Europe.
[2] Federico Silla,et al. Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.
[3] Mark G. Karpovsky,et al. Application of network calculus to general topologies using turn-prohibition , 2002, Proceedings.Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies.
[4] Johnny Öberg,et al. Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[5] José Duato,et al. An Efficient Implementation of Distributed Routing Algorithms for NoCs , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).
[6] Mahmood Fathy,et al. Reliable NoC architecture utilizing a robust rerouting algorithm , 2008, Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08).
[7] Qiang Xu,et al. On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[8] Doug A. Edwards,et al. Adaptive stochastic routing in fault-tolerant on-chip networks , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[9] Marcelo Lubaszewski,et al. Diagnosis of interconnect shorts in mesh NoCs , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[10] M. Ali,et al. A dynamic routing mechanism for network on chip , 2005, 2005 NORCHIP.
[11] Alexandre M. Amory,et al. A scalable test strategy for network-on-chip routers , 2005, IEEE International Conference on Test, 2005..
[12] S. Medardoni,et al. Yield-oriented evaluation methodology of network-on-chip routing implementations , 2009, 2009 International Symposium on System-on-Chip.
[13] Luca Benini,et al. Synthesis of low-overhead configurable source routing tables for network interfaces , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[14] Michele Favalli,et al. Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture , 2011, 2011 Design, Automation & Test in Europe.
[15] Fabien Clermidy,et al. An asynchronous NOC architecture providing low latency service and its multi-level design framework , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.
[16] Shashi Kumar,et al. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures , 2006, SAMOS.
[17] Luca Benini,et al. Reliability Support for On-Chip Memories Using Networks-on-Chip , 2006, 2006 International Conference on Computer Design.
[18] W. Marsden. I and J , 2012 .
[19] David Blaauw,et al. Vicis: A reliable network for unreliable silicon , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[20] José Duato,et al. On the Potentials of Segment-Based Routing for NoCs , 2008, 2008 37th International Conference on Parallel Processing.
[21] Antonio Robles,et al. A routing methodology for achieving fault tolerance in direct networks , 2006, IEEE Transactions on Computers.
[22] Nima Honarmand,et al. A Heuristic Search Algorithm for Re-routing of On-Chip Networks in The Presence of Faulty Links and Switches , 2007 .