Deriving reduced transistor count circuits from AIGs

This paper introduces a methodology to reduce transistor count in circuits mapped using simple gates. The resulting circuits are obtained by combining state-of-the-art optimization tools to minimize the number of nodes in and-inverter graph (AIG) representations, with graph-based algorithms to minimize inverters, efficiently modified to reduce transistor count. This work provides reduced transistor count simple gate implementations that can be adopted as fair reference start-points in further investigations, as they are far more efficient than previously published results using simple gates.

[1]  K. Keutzer DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, 24th ACM/IEEE Design Automation Conference.

[2]  Ricardo Reis,et al.  Associating CMOS transistors with BDD arcs for technology mapping , 1995 .

[3]  Ilaria De Munari,et al.  An evolutionary approach for standard-cell library reduction , 2007, GLSVLSI '07.

[4]  Rajendran Panda,et al.  Library-less synthesis for static CMOS combinational logic circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[5]  Sachin S. Sapatnekar,et al.  BDD decomposition for delay oriented pass transistor logic synthesis , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  André Inácio Reis,et al.  Advanced technology mapping for standard-cell generators , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[7]  Mayler G. A. Martins,et al.  KL-cut based digital circuit remapping , 2012, NORCHIP 2012.

[8]  David Blaauw,et al.  On the decreasing significance of large standard cells in technology mapping , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[9]  Sachin S. Sapatnekar,et al.  DAG based library-free technology mapping , 2007, GLSVLSI '07.

[10]  Randal E. Bryant,et al.  Inverter minimization in multi-level logic networks , 1993, ICCAD.

[11]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[12]  John M. Lewis,et al.  The Node-Deletion Problem for Hereditary Properties is NP-Complete , 1980, J. Comput. Syst. Sci..

[13]  Sachin S. Sapatnekar,et al.  Technology mapping for high-performance static CMOS and pass transistor logic designs , 2001, IEEE Trans. Very Large Scale Integr. Syst..