Throughput Analysis of Synchronous Data Flow Graphs

Synchronous data flow graphs (SDFGs) are a useful tool for modeling and analyzing embedded data flow applications, both in a single processor and a multiprocessing context or for application mapping on platforms. Throughput analysis of these SDFGs is an important step for verifying throughput requirements of concurrent real-time applications, for instance within design-space exploration activities. Analysis of SDFGs can be hard, since the worst-case complexity of analysis algorithms is often high. This is also true for throughput analysis. In particular, many algorithms involve a conversion to another kind of data flow graph, the size of which can be exponentially larger than the size of the original graph. In this paper, we present a method for throughput analysis of SDFGs, based on explicit state-space exploration and we show that the method, despite its worst-case complexity, works well in practice, while existing methods often fail. We demonstrate this by comparing the method with state-of-the-art cycle mean computation algorithms. Moreover, since the state-space exploration method is essentially the same as simulation of the graph, the results of this paper can be easily obtained as a byproduct in existing simulation tools

[1]  Sterling K. Berberian Linear Algebra , 1992 .

[2]  MengChu Zhou,et al.  Multiple-Weighted Marked Graphs , 1993 .

[3]  Sander Stuijk,et al.  Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[4]  Rajesh K. Gupta,et al.  Faster maximum and minimum mean cycle algorithms for system-performance analysis , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Robert E. Tarjan,et al.  Faster parametric shortest path and minimum-balance algorithms , 1991, Networks.

[6]  Richard M. Karp,et al.  A characterization of the minimum cycle mean in a digraph , 1978, Discret. Math..

[7]  Edward A. Lee,et al.  Synthesis of Embedded Software from Synchronous Dataflow Specifications , 1999, J. VLSI Signal Process..

[8]  S. Irani,et al.  Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[9]  Raymond Reiter,et al.  Scheduling Parallel Computations , 1968, J. ACM.

[10]  Sander Stuijk,et al.  Minimising buffer requirements of synchronous dataflow graphs with model checking , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[11]  Ali Dasdan,et al.  Experimental analysis of the fastest optimum cycle ratio and mean algorithms , 2004, TODE.

[12]  J. Quadrat,et al.  Numerical Computation of Spectral Elements in Max-Plus Algebra☆ , 1998 .

[13]  Guang R. Gao,et al.  Rate-optimal schedule for multi-rate DSP computations , 1995, J. VLSI Signal Process..

[14]  E.A. Lee,et al.  Synchronous data flow , 1987, Proceedings of the IEEE.

[15]  Twan Basten,et al.  Task-level timing models for guaranteed performance in multiprocessor networks-on-chip , 2003, CASES '03.

[16]  Joseph Sifakis,et al.  Use of Petri nets for performance evaluation , 1977, Acta Cybern..

[17]  Shuvra S. Bhattacharyya,et al.  Embedded Multiprocessors: Scheduling and Synchronization , 2000 .

[18]  Heinrich Meyr,et al.  Scheduling for optimum data memory compaction in block diagram oriented software synthesis , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[19]  G. G. Stokes "J." , 1890, The New Yale Book of Quotations.

[20]  Giovanni Chiola,et al.  Ergodicity and Throughput Bounds of Petri Nets with Unique Consistent Firing Count Vector , 1991, IEEE Trans. Software Eng..

[21]  S.S. Bhattacharyya,et al.  A hierarchical multiprocessor scheduling system for DSP applications , 1995, Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers.