Partial TMR in FPGAs Using Approximate Logic Circuits

TMR is a very effective technique to mitigate SEU effects in FPGAs, but it is often expensive in terms of FPGA resource utilization and power consumption. For certain applications, Partial TMR can be used to trade off the reliability with the cost of mitigation. In this work we propose a new approach to build Partial TMR circuits for FPGAs using approximate logic circuits. This approach is scalable, with a fine granularity, and can provide a flexible balance between reliability and overheads. The proposed approach has been validated by the results of fault injection experiments and proton irradiation campaigns.

[1]  M. Wirthlin,et al.  SEU-induced persistent error propagation in FPGAs , 2005, IEEE Transactions on Nuclear Science.

[2]  Ricardo Reis,et al.  Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments , 2015, 2015 16th Latin-American Test Symposium (LATS).

[3]  Mayler G. A. Martins,et al.  Methodology for achieving best trade-off of area and fault masking coverage in ATMR , 2014, 2014 15th Latin American Test Workshop - LATW.

[4]  A. Lesea,et al.  Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis , 2008, IEEE Transactions on Nuclear Science.

[5]  L.W. Massengill,et al.  Reducing Soft Error Rate in Logic Circuits Through Approximate Logic Functions , 2006, IEEE Transactions on Nuclear Science.

[6]  Mario García-Valderas,et al.  Logic masking for SET Mitigation Using Approximate Logic Circuits , 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

[7]  M. Wirthlin,et al.  Improving FPGA Design Robustness with Partial TMR , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[8]  Kartik Mohanram,et al.  Low Cost Concurrent Error Masking Using Approximate Logic Circuits , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Michael J. Wirthlin,et al.  Estimating Soft Processor Soft Error Sensitivity through Fault Injection , 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

[10]  Kartik Mohanram,et al.  Approximate logic circuits for low overhead, non-intrusive concurrent error detection , 2008, 2008 Design, Automation and Test in Europe.

[11]  S. Katkoori,et al.  Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs , 2004, IEEE Transactions on Nuclear Science.

[12]  Steven M. Guertin,et al.  Using Benchmarks for Radiation Testing of Microprocessors and FPGAs , 2015, IEEE Transactions on Nuclear Science.

[13]  Adrian Evans,et al.  New approaches for synthesis of redundant combinatorial logic for selective fault tolerance , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[14]  M. Caffrey,et al.  Evaluating TMR Techniques in the Presence of Single Event Upsets , 2003 .

[15]  Dong Sam Ha,et al.  HOPE: an efficient parallel fault simulator for synchronous sequential circuits , 1992, DAC '92.

[16]  Mario García-Valderas,et al.  Error masking with approximate logic circuits using dynamic probability estimations , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[17]  L. Entrena,et al.  Partial TMR in FPGAs Using Approximate Logic Circuits , 2015, 2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

[18]  M. Wirthlin,et al.  Fine-Grain SEU Mitigation for FPGAs Using Partial TMR , 2008, IEEE Transactions on Nuclear Science.

[19]  David Kaeli,et al.  The Use of Benchmarks for High-Reliability Systems , 2015 .

[20]  Luigi Carro,et al.  On the optimal design of triple modular redundancy logic for SRAM-based FPGAs , 2005, Design, Automation and Test in Europe.