Efficient BIST TPG design and test set compaction via input reduction

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

[1]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[2]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[3]  B. Elspas,et al.  The Theory of Autonomous Linear Sequential Networks , 1959 .

[4]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[5]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Edward J. McCluskey,et al.  Circuits for Pseudo-Exhaustive Test Pattern Generation. , 1986 .

[7]  Janusz Rajski,et al.  On necessary and nonconflicting assignments in algorithmic test pattern generation , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  F. Brglez,et al.  A neutral netlists of 10 combinational circuits and a target translator in FORTRAN , 1985 .

[9]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[10]  Janusz Rajski,et al.  The testability-preserving concurrent decomposition and factorization of Boolean expressions , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  S. B. Akers,et al.  On the use of linear sums in exhaustive testing , 1987 .

[12]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  J. Mucha,et al.  Built-In Test for Complex Digital Integrated Circuits , 1979, Fifth European Solid State Circuits Conference - ESSCIRC 79.

[14]  Sandeep K. Gupta,et al.  Test generation and embedding for built-in self-test , 1996 .

[15]  Edward J. McCluskey,et al.  Circuits for pseudoexhaustive test pattern generation , 1986, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  R. Gupta,et al.  Configuring multiple scan chains for minimum test time , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[17]  S. Hellebrand,et al.  An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[18]  Miron Abramovici,et al.  Low-cost redundancy identification for combinational circuits , 1994, Proceedings of 7th International Conference on VLSI Design.

[19]  Sandeep K. Gupta,et al.  Random pattern testable logic synthesis , 1994, ICCAD.

[20]  S. B. Akers,et al.  On the Role of Independent Fault Sets in the Generation of Minimal Test Sets , 1987 .

[21]  Miron Abramovici,et al.  One-pass redundancy identification and removal , 1992, Proceedings International Test Conference 1992.

[22]  Dhiraj K. Pradhan,et al.  Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci , 1992, Proceedings International Test Conference 1992.

[23]  Michael H. Schulz,et al.  Improved deterministic test pattern generation with applications to redundancy identification , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Irith Pomeranz,et al.  3-weight Pseudo-random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Norman J. Pullman.  Clique Covering of Graphs IV. Algorithms , 1984, SIAM J. Comput..

[26]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[27]  Edward J. McCluskey.  Verification Testing - A Pseudoexhaustive Test Technique , 1984, IEEE Trans. Computers.