Reducing cache energy consumption by tag encoding in embedded processors
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[1] Jun Yang,et al. Low cost instruction cache designs for tag comparison elimination , 2003, ISLPED '03.
[2] Larry L. Biro,et al. Power considerations in the design of the Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[3] Frank Vahid,et al. A self-tuning cache architecture for embedded systems , 2004 .
[4] B. Moyer,et al. Instruction fetch energy reduction using loop caches for embedded applications with small tight loops , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).
[5] Alvin M. Despain,et al. Cache designs for energy efficiency , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.
[6] William H. Mangione-Smith,et al. The filter cache: an energy efficient memory structure , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[7] Trevor Mudge,et al. MiBench: A free, commercially representative embedded benchmark suite , 2001 .
[8] Frank Vahid,et al. Energy benefits of a configurable line size cache for embedded systems , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..
[9] Frank Vahid,et al. A way-halting cache for low-energy high-performance systems , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[10] Shanq-Jang Ruan,et al. Design and analysis of low-power cache using two-level filter scheme , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[11] Alexander V. Veidenbaum,et al. Reducing power consumption for high-associativity data caches in embedded processors , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[12] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[13] Peter Petrov,et al. Tag compression for low power in dynamically customizable embedded processors , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Chia-Lin Yang,et al. HotSpot cache: joint temporal and spatial locality exploitation for I-cache energy reduction , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[15] Richard T. Witek,et al. A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[16] Kazuaki Murakami,et al. Way-predicting set-associative cache for high performance and low energy consumption , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).
[17] Hsien-Hsin S. Lee,et al. Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning , 2003, ISLPED '03.