Implementation of HSSec: a high-speed cryptographic co-processor

In this paper a high-speed cryptographic coprocessor, named HSSec, is presented. The core embeds two hash functions, SHA-1 and SHA-512, and the symmetric block cipher AES. The architecture of HSSec renders it suitable for widely spread applications with security demands. The presented co-processor can be used in every system integrating standards such as IPSec or the upcoming JPSec and P1619. The main characteristic of the proposed implementation is common use of the available resources, to minimize further area requirements. Additionally the cryptographic primitives can operate in parallel, providing high throughput whenever needed. Finally the system can operate in ECB or CBC modes. The HSSec co-processor has relatively small area and its performance reaches 1 Gbps (AES, SHA-1 and SHA-512) for XILINX's Virtex II FPGA family.

[1]  A.P. Kakarountas,et al.  A high-throughput area efficient FPGA implementation of AES-128 Encryption , 2005, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..

[2]  尚弘 島影 National Institute of Standards and Technologyにおける超伝導研究及び生活 , 2001 .

[3]  I. Yiakoumis,et al.  Efficient Small-Sized Implementation of the Keyed-Hash Message Authentication Code , 2005, EUROCON 2005 - The International Conference on "Computer as a Tool".

[4]  Vania Conan,et al.  A proposal for supporting selective encryption in JPSEC , 2003, IEEE Trans. Consumer Electron..

[5]  Sandra Dominikus,et al.  A Highly Regular and Scalable AES Hardware Architecture , 2003, IEEE Trans. Computers.

[6]  Vincent Rijmen,et al.  The Design of Rijndael , 2002, Information Security and Cryptography.

[7]  Constantinos E. Goutis,et al.  A low-power and high-throughput implementation of the SHA-1 hash function , 2005, 2005 IEEE International Symposium on Circuits and Systems.