Alternative Architectures Toward Reliable Memristive Crossbar Memories

Resistive random access memory (ReRAM), referred to as memristor, is an emerging memory technology to potentially replace conventional memories, which will soon be facing serious design challenges related to continued scaling. Memristor-based crossbar architecture has been shown to be the best implementation for ReRAM. However, it faces a major challenge related to the sneak current (current sneak paths) flowing through unselected memory cells, which significantly reduces the voltage read margins. In this paper, five alternative architectures (topologies) are applied to minimize the impact of sneak current; the architectures are based on the introduction of insulating junctions within the crossbar. Simulations that were performed while considering different memory accessing aspects, such as bit reading versus word reading, stored data background distribution, crossbar dimensions, etc., showed that read margins can be increased significantly (up to 4×) as compared with standard crossbar architectures. In addition, the proposed architectures eliminate the requirement for extra select devices at each cross point and have no operational complexity overhead.

[1]  Shimeng Yu,et al.  Metal–Oxide RRAM , 2012, Proceedings of the IEEE.

[2]  R. Waser,et al.  Integrated Complementary Resistive Switches for Passive High-Density Nanocrossbar Arrays , 2011, IEEE Electron Device Letters.

[3]  Rainer Waser,et al.  Complementary resistive switches for passive nanocrossbar memories. , 2010, Nature materials.

[4]  G. C. Sirakoulis,et al.  A Novel Design and Modeling Paradigm for Memristor-Based Crossbar Circuits , 2012, IEEE Transactions on Nanotechnology.

[5]  Wei Yi,et al.  AC sense technique for memristor crossbar , 2012 .

[6]  Said F. Al-Sarawi,et al.  An Analytical Approach for Memristive Nanoarchitectures , 2011, IEEE Transactions on Nanotechnology.

[7]  Byung Joon Choi,et al.  Engineering nonlinearity into memristors for passive crossbar applications , 2012 .

[8]  J. Yang,et al.  State Dynamics and Modeling of Tantalum Oxide Memristors , 2013, IEEE Transactions on Electron Devices.

[9]  Georgios Ch. Sirakoulis,et al.  Memristor based memories: Technology, design and test , 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

[10]  Seungjun Kim,et al.  Flexible memristive memory array on plastic substrates. , 2011, Nano letters.

[11]  Gregory S. Snider,et al.  A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology , 1998 .

[12]  Said Hamdioui,et al.  Testing Open Defects in Memristor-Based Memories , 2015, IEEE Transactions on Computers.

[13]  Narayan Srinivasa,et al.  A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. , 2012, Nano letters.

[14]  Kyeong-Sik Min,et al.  Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array , 2012, IEEE Transactions on Nanotechnology.

[15]  Leon O. Chua.  Resistance switching memories are memristors , 2011 .

[16]  R. Rosezin,et al.  High density 3D memory architecture based on the resistive switching effect , 2009 .

[17]  Anne-Claire Salaün,et al.  Fabrication and electrical characterization of silicon nanowires based resistors , 2009 .

[18]  Wei Zhang,et al.  Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Dmitri B Strukov,et al.  Four-dimensional address topology for circuits with stacked multilayer crossbar arrays , 2009, Proceedings of the National Academy of Sciences.

[20]  T.G. Noll,et al.  Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[21]  Jeyavijayan Rajendran,et al.  Design Considerations for Multilevel CMOS/Nano Memristive Memory , 2012, JETC.

[22]  Tung-Ming Pan,et al.  Improved Resistance Switching Characteristics in Ti-Doped $\hbox{Yb}_{2}\hbox{O}_{3}$ for Resistive Nonvolatile Memory Devices , 2012, IEEE Electron Device Letters.

[23]  Kuo-Pin Chang,et al.  A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts , 2012, 2012 International Electron Devices Meeting.

[24]  L. Chua.  Memristor-The missing circuit element , 1971 .

[25]  Georgios Ch. Sirakoulis,et al.  Improved read voltage margins with alternative topologies for memristor-based crossbar memories , 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

[26]  P. Vontobel,et al.  Writing to and reading from a nano-scale crossbar memory based on memristors , 2009, Nanotechnology.

[27]  Jiale Liang,et al.  Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies , 2010, IEEE Transactions on Electron Devices.

[28]  Peng Li,et al.  Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  Shimeng Yu,et al.  HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector , 2012, 2012 International Electron Devices Meeting.

[30]  J. Yang,et al.  Switching dynamics in titanium dioxide memristive devices , 2009 .

[31]  Sachhidh Kannan,et al.  Sneak-path Testing of Memristor-based Memories , 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

[32]  Khaled N. Salama,et al.  Memristor-based memory: The sneak paths problem and solutions , 2013, Microelectron. J..

[33]  R. Waser,et al.  A Novel Reference Scheme for Reading Passive Resistive Crossbar Memories , 2006, IEEE Transactions on Nanotechnology.

[34]  Mircea R. Stan,et al.  CMOS/nano co-design for crossbar-based molecular electronic systems , 2003 .