On parallelization of circuit simulation SPICE3 using multithreaded programming techniques

With an enlarging community using electronic design automation, it is a prominent challenge to provide simulation program with integrated circuit emphasis (SPICE) users with sophisticated integrated circuit (IC) models, since many analog IC manufacturers provide software models in SPICE format. Multi-core technology-based processors deliver better performance-to-cost ratios relative to their single-core predecessors through on-chip multithreading. In this article, we present a parallel version of a SPICE3 circuit simulator using two well-known shared-memory multithread programming interfaces. Two approaches in multithread programming has been considered and proposed to parallelize SPICE3 programs in shared-memory multiprocessor systems. Also, OpenMP and Pthreads libraries are considered to realize the proposed approaches that are used to redesign the SPICE3 device-loading functions. Case studies using SRAM circuits as input data were investigated. They consist of MOS devices modeled using BSIM3 models. Performance results from multi-core multiprocessor-based servers exhibit performance improvement of multithreaded implementation over the original version of SPICE3 circuit simulator.

[1]  Qinghua Zheng,et al.  Parallel harmonic balance , 1993, VLSI.

[2]  Yuhua Cheng,et al.  MOSFET Modeling and Bsim3 User's Guide , 1999 .

[3]  New Mexico..  for Sandia National Laboratories , 2009 .

[4]  R.A. Rohrer.  Circuit simulation-the early years , 1992, IEEE Circuits and Devices Magazine.

[5]  Shyh-Jye Jou,et al.  A parallel event-driven MOS timing simulator on distributed-memory multiprocessors , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[6]  C.-J. Richard Shi,et al.  Hierarchical multi-dimensional table lookup for model compiler based circuit simulation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  Werner John,et al.  Circuit partitioning for waveform relaxation , 1991, Proceedings of the European Conference on Design Automation..

[8]  Qinghua Zheng,et al.  A new approach for parallel simulation of VLSI circuits on a transistor level , 1998 .

[9]  Wei Dong,et al.  A Parallel Harmonic-Balance Approach to Steady-State and Envelope-Following Simulation of Driven and Autonomous Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Barbara M. Chapman,et al.  OpenMP Implementation of SPICE3 Circuit Simulator , 2007, International Journal of Parallel Programming.

[12]  Goichi Yokomizo,et al.  A parallel and accelerated circuit simulator with precise accuracy , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[13]  TWO-WEEK Loan COpy,et al.  University of California , 1886, The American journal of dental science.

[14]  Chung-Kuan Cheng,et al.  Parallel transistor level circuit simulation using domain decomposition methods , 2009, 2009 Asia and South Pacific Design Automation Conference.