An analytical model relating FPGA architecture and place and route runtime

This paper presents an analytical model that relates the architectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a simulated annealing based placement algorithm employing a bounding-box wirelength cost function, and a negotiationbased A* router. We also show an example application of the model in early architecture evaluation.

[1]  Judea Pearl,et al.  Heuristics : intelligent search strategies for computer problem solving , 1984 .

[2]  Scott Hauck,et al.  Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation , 2007 .

[3]  Jonathan Rose,et al.  A stochastic model to predict the routability of field-programmable gate arrays , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Jonathan Rose,et al.  Modeling routing demand for early-stage FPGA architecture development , 2008, FPGA '08.

[5]  Steven J. E. Wilton,et al.  Wirelength modeling for homogeneous and heterogeneous FPGA architectural development , 2009, FPGA '09.

[6]  Vaughn Betz,et al.  A fast routability-driven router for FPGAs , 1998, FPGA '98.

[7]  Wayne Luk,et al.  An analytical model describing the relationships between logic architecture and FPGA density , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[8]  Kenneth B. Kent,et al.  VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling , 2011, TRETS.

[9]  Vaughn Betz,et al.  High-quality, deterministic parallel placement for FPGAs on commodity hardware , 2008, FPGA '08.

[10]  Mike Hutton,et al.  Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation , 2003, SLIP '03.

[11]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[12]  D. Mitra,et al.  Convergence and finite-time behavior of simulated annealing , 1985, 1985 24th IEEE Conference on Decision and Control.

[13]  John Gaschnig,et al.  Exactly How Good Are Heuristics?: Toward a Realistic Predictive Theory of Best-First Search , 1977, IJCAI.

[14]  Dinesh Bhatia,et al.  On metrics for comparing interconnect estimation methods for FPGAs , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Yintang Yang,et al.  Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations , 2005, Sixth international symposium on quality electronic design (isqed'05).