A Systematic Design Methodology of Asynchronous SAR ADCs

Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent power efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also hard to quickly evaluate the feasibility of a given specification in a process node. This paper presents a systematic sizing procedure for asynchronous SAR ADCs based on design considerations. A sizing tool based on the proposed design procedure is also implemented, the sizing results of which are highly competitive in comparison with other state-of-the-art manual works. Moreover, the sizing time is relatively short due to the efficient and effective search algorithms employed. In addition to the simulation results, two silicon proofs with different specifications and process nodes are provided to demonstrate the feasibility of this design methodology.

[1]  Robert W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS , 2006 .

[2]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[3]  J.L. Huertas,et al.  Flexible silicon compilation of charge redistribution data conversion systems , 1991, [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems.

[4]  N. P. van der Meijs,et al.  A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios , 2011, IEEE Journal of Solid-State Circuits.

[5]  Jon Guerber,et al.  Merged capacitor switching based SAR ADC with highest switching energy-efficiency , 2010 .

[6]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[7]  Marce Eleccion,et al.  A/D and D/A converters , 1972, IEEE Spectrum.

[8]  Euisik Yoon,et al.  A 0.5V 20fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[9]  Eric A. M. Klumperink,et al.  A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  Un-Ku Moon,et al.  A 10b Ternary SAR ADC with decision time quantization based redundancy , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[11]  Denis C. Daly,et al.  A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy , 2009, IEEE Journal of Solid-State Circuits.

[12]  Soon-Jyh Chang,et al.  A power-efficient sizing methodology of SAR ADCs , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[13]  Soon-Jyh Chang,et al.  A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications , 2012, IEEE Journal of Solid-State Circuits.

[14]  Jose E. Franca,et al.  Framework for architecture synthesis of data conversion systems employing binary-weighted capacitor arrays , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[15]  Jose E. Franca,et al.  Automatic multi-level macromodel generation for data conversion systems employing binary-weighted capacitor-arrays , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[16]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[17]  Kiat Seng Yeo,et al.  An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  Daehwa Paik,et al.  A low-noise self-calibrating dynamic comparator for high-speed ADCs , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[19]  Eisse Mensink,et al.  A Low-Offset Double-Tail Latch-Type Voltage Sense Amplifier , 2007 .

[20]  M. S. Tawfik,et al.  HiFADiCC: a prototype framework of a highly flexible analog to digital converters silicon compiler , 1990, IEEE International Symposium on Circuits and Systems.

[21]  T. Nirschl,et al.  Yield and speed optimization of a latch-type voltage sense amplifier , 2004, IEEE Journal of Solid-State Circuits.

[22]  Jai-Ming Lin,et al.  Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Li-Rong Zheng,et al.  Mismatch aware power and area optimization of successive-approximation ADCs , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

[24]  Chorng-Kuang Wang,et al.  A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[25]  Nuno Horta,et al.  State-of-the-Art on Automatic Analog IC Sizing , 2014 .

[26]  P. Gray,et al.  All-MOS charge redistribution analog-to-digital conversion techniques. I , 1975, IEEE Journal of Solid-State Circuits.

[27]  Mark Po-Hung Lin,et al.  Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[28]  G. Ruan.  A behavioral model of A/D converters using a mixed-mode simulator , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[29]  R.W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS , 2006, IEEE Journal of Solid-State Circuits.

[30]  Robert H. Walden,et al.  Analog-to-digital converter survey and analysis , 1999, IEEE J. Sel. Areas Commun..

[31]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[32]  Soon-Jyh Chang,et al.  10-bit 30-MS/s SAR ADC Using a Switchback Switching Method , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[33]  Nobukazu Takai,et al.  Non-binary SAR ADC with digital error correction for low power applications , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.