Optimization Design for VLSI Layout with Neural Networks

We study optimization design method that aims at the unit layout in automation design process for integrated circuit. We take one dimensional logic gate as a design exampleBy using neural networks and Hopfield neural unit model,we bulid energy function to seek the best value among all extremums with simulated annealing algorithm, to attain demand that the total length of all connect lines among various logic gates is the shortest,and to increase optimization degree of layout optimization design