Design and Simulation for NBTI Aware Logic Gates

Reliability of the electronic circuits is one of the most prominent factor in the development of very large-scale integration (VLSI) industry. Huge demand for compact size and high performance of electronic devices leads the excessive scaling of the transistor. Aggressive scaling of transistor in ultra-deep submicron regime arises the problem of short channel effects (SCEs) which is the major reason for subthreshold leakage and reliability issues. Negative input voltage to p-channel metal oxide semiconductor (PMOS) transistor causes interface traps at silicon dioxide and silicon substrate interface which leads to increase in the threshold voltage of the transistor and degrades the circuit performance. The design parameters exceed the design specification and causes the variations in timing due to negative bias temperature instability (NBTI) degradation that results logic failure. This paper presents the impact of reliability variations on 32 nm complementary metal oxide semiconductor (CMOS) predictive technology model (PTM) and 20 nm multi-gate PTM fin-shaped field effect transistor (FinFET) circuits. NBTI degradation of various circuits are evaluated with the help of Cadence’s virtuoso tool containing Spectre native reliability simulator. Simulation results are showing that NBTI degradation causes variations in threshold voltage and alters the output performance.

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