Efficient Fine-Grain Synchronization on a Multi-Core Chip Architecture: A Fresh Look

Multi-core chip architectures are becoming mainstream, pe rmitting increasing on-chip parallelism through hardware support for multithreading. Finegrain synchronization is essential to the effective utilization of the capacity provided by future hi g -performance multi-core architectures. However, there are also new challenges realizing such fine-g rain synchronization in large-scale multi-core chip architectures – such as the IBM Cyclops-64 c hip that contains more than 100 processing cores and employs a memory organization with explic itly addressable memory segments instead of data cache. This paper presents a fresh look at the challenges and propos es a scalable solution for fine-grain synchronization that efficiently enforces mutual exclusion andread-after-write data-dependencies between concurrent threads. Using the Cyclops-64 chip arch itecture as a case study, we illustrate how to use a small Synchronization State Buffer (SSB) associated with each memory bank to accelerate the fine-grain synchronization by recording and managin g the states of frequently synchronized data units with modest hardware extensions. We demonstrate the effectiveness and efficiency of the proposed solution. • For mutual exclusion: Using distributed fine-grain locking at each of the memory u nits, we avoid the unnecessary serialization of operations on diffe rent elements of the same concurrent data structure and achieve this goal efficiently. • For read-after-write data-dependencies synchronization: our method encourages the exploration of do-across style of loop-level parallelism where loop-carried data dependencies can often be directly implemented by the application of the finegrain synchronization operations and the removal of useless barriers. The experimental results demonstrate significant performa nce gain due to the use of the above fine-grain synchronization solutions.