CMOS clock buffer with reduced supply noise sensitivity

A CMOS clock buffer that minimises the period jitter due to supply noise is presented. The proposed buffer features a highpass noise cancellation circuit which is able to halve the output period jitter compared to a standard CMOS buffer. By avoiding large decoupling capacitors to filter out the supply noise, this technique enables a more efficient use of the active area when compared to traditional jitter reduction techniques. The additional current consumption for the noise cancellation circuit is a fraction (up to 10%) of the amount of current allocated to the clock buffer.