Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Abstract This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

[1]  Xiaoqing Wen,et al.  Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS , 2018, IEEE Transactions on Emerging Topics in Computing.

[2]  Xin Liu,et al.  Multiple Node Upset-Tolerant Latch Design , 2019, IEEE Transactions on Device and Materials Reliability.

[3]  Hai Huang,et al.  Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Spyros Tragoudas,et al.  Radiation Hardened Latch Designs for Double and Triple Node Upsets , 2017, IEEE Transactions on Emerging Topics in Computing.

[5]  Yang Zhao,et al.  A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology , 2021, IEEE Transactions on Emerging Topics in Computing.

[6]  Massimo Alioto,et al.  Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Jie Li,et al.  High Robust and Low Cost Soft Error Hardened Latch Design for Nanoscale CMOS Technology , 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

[8]  Xin Xie,et al.  A novel self-recoverable and triple nodes upset resilience DICE latch , 2018, IEICE Electron. Express.

[9]  J. Furuta,et al.  A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI , 2014, IEEE Transactions on Nuclear Science.

[10]  Vojin G. Oklobdzija,et al.  Low-Power Soft Error Hardened Latch , 2009, PATMOS.

[11]  Mahdi Fazeli,et al.  Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation , 2013, Microelectron. Reliab..

[12]  Bulusu Anand,et al.  A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design , 2019, IEEE Transactions on Nuclear Science.

[13]  Xiaoxuan She,et al.  Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation , 2009, IEEE Transactions on Nuclear Science.

[14]  Hai Huang,et al.  Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Kiamal Z. Pekmestzi,et al.  DIRT latch: A novel low cost double node upset tolerant latch , 2017, Microelectron. Reliab..

[16]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[17]  Yuanqing Li,et al.  Double Node Upsets Hardened Latch Circuits , 2015, J. Electron. Test..

[18]  Huaguo Liang,et al.  A High Performance SEU Tolerant Latch , 2015, J. Electron. Test..

[19]  Kohei Miyase,et al.  Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments , 2020, IEEE Transactions on Aerospace and Electronic Systems.

[20]  Jun Xiao,et al.  Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Huaguo Liang,et al.  Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Huaguo Liang,et al.  Design of a Radiation Hardened Latch for Low-Power Circuits , 2014, 2014 IEEE 23rd Asian Test Symposium.

[23]  Qiang Zhao,et al.  Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Kiamal Z. Pekmestzi,et al.  DONUT: A Double Node Upset Tolerant Latch , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

[25]  Jie Song,et al.  Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[26]  Ahmad Patooghy,et al.  Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies , 2009, IET Comput. Digit. Tech..

[27]  Fabrizio Lombardi,et al.  F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments , 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[28]  Bingbing Xia,et al.  Design and Comparison of High-Reliable Radiation-Hardened Flip-Flops Under SMIC 40nm Process , 2016, J. Circuits Syst. Comput..

[29]  Mahdi Fazeli,et al.  Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations , 2015, J. Circuits Syst. Comput..

[30]  Huaguo Liang,et al.  A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology , 2015, IEICE Trans. Electron..