Variable-rate pipelined multiplier design for reconfigurable DSP applications

This paper presents a VLSI design and implementation of a variable-rate multiply-and-accumulate (MAC) block for DSP applications. The pipeline depth of the multiplier is dynamically controlled given the throughput requirement of the application. The depth of pipeline varies at the hardware level which controls the rate of execution to save power consumption. The MAC is targeted for a coarse grain FPGA design to support a wide range of digital signal processing applications. The power consumption is lowered by reducing the unnecessary register switching. The technique is applied to carry-save and Booth recoded multipliers. The MAC circuit is designed in 0.35-/spl mu/m CMOS processing technology and evaluated for current DSP applications.