An FPGA based generic framework for high speed sum of absolute difference implementation

In this paper we present a hardware architecture for the Sum of Absolute Difference (SAD) technique. This paper also gives the design details and the implementation results for an FPGA based core that permits realisation of a high speed matching algorithm for real time image processing applications. The matching criterion chosen is the SAD algorithm The implementation provides the correct position of the target within the frame/image. The ease of implementation lies in the fact that the core is highly parameterized and therefore can cater effectively to the needs of different sizes and resolutions of images and filters. The high speed and the low area of silicon usage make it useful for a number of image processing applications. The paper also gives a review of different hardware architectures. © EuroJournals Publishing, Inc. 2009.

[1]  Wang Qin,et al.  A High-Performance Low Cost SAD Architecture for Video Coding , 2007, IEEE Transactions on Consumer Electronics.

[2]  Peter Lee,et al.  An FPGA implementation of a flexible, parallel image processing architecture suitable for embedded vision systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[3]  Timo Hämäläinen,et al.  A High-Performance Sum of Absolute Difference Implementation for Motion Estimation , 2006, IEEE Transactions on Circuits and Systems for Video Technology.

[4]  Stamatis Vassiliadis,et al.  A sum of absolute differences implementation in FPGA hardware , 2002, Proceedings. 28th Euromicro Conference.

[5]  Graham A. Jullien,et al.  On the use of 4:2 compressors for partial product reduction , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[6]  Andreas Steininger,et al.  Hardware implementation of an SAD based stereo vision algorithm , 2007, 2007 IEEE Conference on Computer Vision and Pattern Recognition.

[7]  Cao Wei,et al.  A novel SAD computing hardware architecture for variable-size block motion estimation and its implementation with FPGA , 2003, ASICON 2003.

[8]  Yücel Altunbasak,et al.  SAD reuse in hierarchical motion estimation for the H.264 encoder , 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

[9]  Antonio Ortega,et al.  Probabilistic partial-distance fast matching algorithms for motion estimation , 2001, IEEE Trans. Circuits Syst. Video Technol..

[10]  Ville Lappalainen,et al.  Architectures for the sum of absolute differences operation , 2002, IEEE Workshop on Signal Processing Systems.

[11]  José-Luis Sánchez-Romero,et al.  Partial product reduction based on look-up tables , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).