SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors
暂无分享,去创建一个
[1] M. Yamaoka,et al. Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[2] S. Maegawa,et al. Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[3] S. Shimada,et al. Low-power embedded SRAM modules with expanded margins for writing , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[4] M.J.M. Pelgrom,et al. Matching properties of MOS transistors , 1989 .
[5] S. Shimada,et al. A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor , 2004, IEEE Journal of Solid-State Circuits.
[6] E. Seevinck,et al. Static-noise margin analysis of MOS SRAM cells , 1987 .
[7] N. Maeda,et al. A 300MHz 25/spl mu/A/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[8] Yasuhisa Shimazaki,et al. A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor , 2004, IEEE Journal of Solid-State Circuits.