On Optimized FPGA Implementations of the SHA-3 Candidate Groestl

Actual and future developments of the automotive market (e.g. the AUTOSAR project or car2car communication systems) will increase the need for a suitable cryptographic infrastructure in modern vehicles. A core component for such a generic cryptographic core is a secure cryptographic hash function, because these functions are the base for a lot of applications like challenge-reponse authentication systems and digital signature schemes. In the present paper we evaluate the SHA-3 candidate Grostl with respect to area requirements, which play a very important role for cost-sensitive markets. The National Institute of Standards and Technology (NIST) has started a competition for a new secure hash standard. In this context third party implementations of all proposed hash functions are regarded as an important part of the competition. We chose to implement the Grostl hash function for FPGAs, for its resemblance to AES. More precisely we developed two optimized versions, one optimized for throughput, the other one for area. Both implementations improve the results and estimates presented in the original submission to the competition. The performance of both implementations may be improved further, thus Grostl seems to be a good candidate for implementations on medium sized FPGAs. Besides that, it is shown that Grostl needs a significant amount of resources, which will hinder its use for automotive applications.