Leakage Power Optimization in Set-associative Caches

The leakage power issue is challenging high-performance microprocessor design, especially as feature size shrinks. Caches represent a sizable fraction of the total power consumption. Chipmakers have proposed many low leak design techniques, in which gated-vdd and cache decay are the most efficient circuit and architectural methods. Cache decay are based on counter overflow, and lose many low leak opportunities. In this paper, we use existing LRU information to aggressively clamp cache blocks, complementing the counter-based mechanism (we call it LRU-assist algorithm). Simulation results show that, with little hardware cost and negligible performance loss(0.1%), LRU-assist decay can shut off 53% cache lines on average and greatly decrease the leakage power dissipation.