An 8 GSps 14 bit RF DAC With IM3<−62 dBc up to 3.6 GHz
暂无分享,去创建一个
Jian Luan | Xinyu Liu | Lei Zhou | Xuan Guo | Dong Wang | Danyu Wu | Jin Wu | Huasen Liu | Chonghe Ma | Jinxin Xue | Danyu Wu | Lei Zhou | Xinyu Liu | Jinxin Xue | Xuan Guo | Jin Wu | Jian Luan | Dong Wang | Huasen Liu | Chonghe Ma
[1] Tai-Haur Kuo,et al. A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[2] Brian Miller,et al. A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz ${\rm f}_{\rm T}$ BiCMOS Process , 2012, IEEE Journal of Solid-State Circuits.
[3] Gil Engel,et al. RF digital-to-analog converters enable direct synthesis of communications signals , 2012, IEEE Communications Magazine.
[4] Gil Engel,et al. A 14b 3/6GHz current-steering RF DAC in 0.18μm CMOS with 66dB ACLR at 2.9GHz , 2012, 2012 IEEE International Solid-State Circuits Conference.
[5] Ko-Chi Kuo,et al. A Switching Sequence for Linear Gradient Error Compensation in the DAC Design , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.
[6] Xiaodong Liu,et al. A 12b 2.9GS/s DAC with IM3 ≪−60dBc beyond 1GHz in 65nm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[7] Ian Galton,et al. A Low-Complexity Dynamic Element Matching DAC for Direct Digital Synthesis , 1998 .
[8] Tai-Haur Kuo,et al. A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection , 2012, IEEE Journal of Solid-State Circuits.
[9] Mark Weaver,et al. A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz , 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).
[10] Lei Zhou,et al. A 30Gsps 6bit DAC in SiGe BiCMOS technology , 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).
[11] Chun-Huat Heng,et al. High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[12] Jin Wu,et al. A 2GSps 12bit DAC with SFDR >57.5dBc up to Nyquist bandwidth , 2013, 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM).
[13] Robert H. M. van Veldhoven,et al. A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping , 2011, IEEE Journal of Solid-State Circuits.
[14] Kok Lim Chan,et al. A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquilst band , 2007, 2007 IEEE Symposium on VLSI Circuits.
[15] Arthur H. M. van Roermund,et al. A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Haiyang Zhu,et al. A 16-bit 10Gsps current steering RF DAC in 65nm CMOS achieving 65dBc ACLR multi-carrier performance at 4.5GHz Fout , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).
[17] Tai-Haur Kuo,et al. A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique , 2014, IEEE Journal of Solid-State Circuits.
[18] Ian Galton,et al. Why Dynamic-Element-Matching DACs Work , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.
[19] Jieh-Tsorng Wu,et al. A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With $ > $70 dB SFDR up to 500 MHz , 2011, IEEE Journal of Solid-State Circuits.
[20] Harrie Gunnink,et al. 11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).