Cross domain protection analysis and verification using whole chip ESD simulation

A whole-chip simulation methodology of the full ESD paths including the full-chip power and ground wiring network has been established, and successfully demonstrated on products with several hundreds of pins. By checking voltage stress across cross domain circuits itself, marginal cross domain ESD design window in sub-100nm SoCs can be extended.

[1]  Fumihiro Minami,et al.  Full-chip analysis method of ESD protection network , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[2]  T. Smedes,et al.  Automatic layout based verification of electrostatic discharge paths , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[3]  Elyse Rosenbaum,et al.  UVeriESD: An ESD verification tool for SoC design , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[4]  Doris Schmitt-Landsiedel,et al.  ESD full chip simulation: HBM and CDM requirements and simulation approach , 2008 .

[5]  M. Okushima.  ESD protection design for mixed-power domains in 90nm CMOS with new efficient power clamp and GND current trigger (GCT) technique , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.