Internal thermal resistance of a multi-chip packaging design for VLSI-based systems

A heat-transfer study is conducted to determine the steady-state internal thermal resistance of a multichip package for VLSI-based systems. The technology, which is known as advanced VLSI packaging (AVP), has flip-chip-soldered chips interconnected on a silicon substrate. AVPs thermal management approach is to dissipate chip power through the silicon substrate to a heat sink or other packaging levels. A three-dimensional heat-conduction analysis is described that characterizes the chip-to-substrate interface. The thermal performance of typical AVP assemblies, which is affected by thermal vias, solder-bump heights, high-power I/O drivers, and chip sizes, is simulated. The internal resistances of an experimental package consisting of three WE32100 chips are analyzed and measured. The predicted values are 3.7, 4.7, and 5.0 degrees C/W, respectively, which is confirmed by the experimental data.<<ETX>>