论文信息 - Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

Ming-Dou Ker | Yeong-Jar Chang | Po-Yen Chiu | Fu-Yi Tsai

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