论文信息 - A high speed CMOS/SOS implementation of a bit level systolic correlator

A high speed CMOS/SOS implementation of a bit level systolic correlator

The fabrication and performance of the first bit level systolic correlator array is described. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64 stage correlation for 1 bit reference and 4 bit data.

John V. McCanny | J. G. McWhirter | A.P.H. McCabe | J. C. White | R. A. Evans

[1] Ian Sinclair. Integrated Circuits , 1983 .

[2] John V. McCanny,et al. Implementation of signal processing functions using 1-bit systolic arrays , 1982 .

[3] J. Blackmer,et al. A 200 Million Operations Per Second (MOPS) Systolic Processor , 1982, Optics & Photonics.

[4] A. Corry,et al. Architecture of a CMOS correlator , 1983 .