A low power VLIW processor generation method by means of extracting non-redundant activation conditions

This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is important for the best power reduction by clock gating to create control signals that can completely shut off redundant clock supplies for registers. In order to generate the control signals automatically, the proposed method utilizes highlevel architecture information called Micro-Operation Descriptions, which describes a VLIW processor architecture. Exploiting the Micro-Operation Descriptions in a VLIW processor generation process, the proposed method automatically extracts the non-redundant activation conditions that can control clock gating to supply the minimum clocks to the pipeline registers. Using the non-redundant activation condition extraction, the proposed method achieves short calculation time and low area overhead; the proposed method can be applied to VLIW processor generation. Experimental results show that the VLIW processor generated with proposed method achieves power reduction about 60% compared to the non-clock-gated VLIW processor, and about 35% compared to the VLIW processor that is applied clock gating by PowerCompiler with negligible area overhead.

[1]  Massoud Pedram,et al.  Power Aware Design Methodologies , 2002 .

[2]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[3]  Luca Benini,et al.  Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers , 1999, TODE.

[4]  Rainer Leupers,et al.  Automatic ADL-based Operand Isolation for Embedded Processors , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[5]  Takashi Kambe,et al.  A method of redundant clocking detection and power reduction at RT level design , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[6]  Tomás Lang,et al.  Individual flip-flops with gated clocks for low power datapaths , 1997 .

[7]  Luca Benini,et al.  A scalable algorithm for RTL insertion of gated clocks based on ODCs computation , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Paolo Ienne,et al.  A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units , 2002, 15th International Symposium on System Synthesis, 2002..

[9]  G. de Veciana,et al.  Exploring performance tradeoffs for clustered VLIW ASIPs , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[10]  Luca Benini,et al.  Transformation and synthesis of FSMs for low-power gated-clock implementation , 1995, ISLPED '95.

[11]  Yoshinori Takeuchi,et al.  Synthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa) , 2000 .

[12]  Narayanan Vijaykrishnan,et al.  A clock power model to evaluate impact of architectural and technology optimizations , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Andreas Wortmann,et al.  The impact of clock gating schemes on the power dissipation of synthesizable register files , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[14]  Yuki Kobayashi,et al.  Synthesizable HDL generation method for configurable VLIW processors , 2004 .