Logical time: specification vs. implementation

MARTE/CCSL specifications express chronological and causal relations on UML models. In a previous work, we proposed a mechanism to verify Esterel implementations against MARTE/CCSL specifications. The mechanism was thought to be general enough to be extended to other languages. However, preserving the polychronous semantics of CCSL was pretty easy with a synchronous language but is much harder when the target language does not directly support coincidence/simultaneity. We show here how coincidence can be encoded. The process is illustrated using VHDL

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